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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH1622601
18-Bit Universal Bus Transceiver With 3-State Outputs
Product Features
* * * * * * * * * PI74ALVCH1622601is designed for low voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25C Inputs/Outputs have equivalent 26 series resistors, no external resistors are required. Bus Hold retains last active bus state during 3-state eliminates the need for external pullup resistors Industrial operation at -40C to +85C Packages available: - 56-pin 240 mil wide plastic TSSOP (A) - 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor's PI74ALVCH series of logic circuits are produced in the Company's advanced 0.5 micron CMOS technology, achieving industry leading speed. The PI74ALVCH1622601 uses D-type latches and D-type flipflops with 3-state outputs to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latched Enable (LEAB and LEBA), and Clock (CLKAB and CLKBA) inputs. The clock can be controlled by the Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA. To reduce overshoot and undershoot, the inputs/outputs include 26 series resistors. To ensure the high-impedance state during power up or power down, OE should be tied to Vcc through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Logic Block Diagram
The PI74ALVCH1622601 has "Bus Hold" which retains the data input's last state whenever the data input goes to high-impedance preventing "floating" inputs and eliminating the need for pullup/ down resistors.
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PS8115B
02/03/98
Product Pin Description
Pin Name CLKEN OE LE CLK Ax Bx GND VCC Description Clock Enable Input (Active LOW) Output Enable Input (Active LOW) Latch Enable (Active HIGH) Clock Input (Active HIGH) Data I/O Data I/O Ground Power
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PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER
Truth Table(1)
CLKENAB X X X H H L L L L Inputs OEAB LEAB H X L H L H L L L L L L L L L L L L CLKAB X X S X X L H A X L H X X L H X X Output B Z L H B0 B0 L H B0 B0
Product Pin Configuration
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 56-PIN 50 A-56 49
V-56
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
Notes: 1. H = High Signal Level L = Low Signal Level Z = High Impedance = LOW-to-HIGH Transition A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Output level before the indicated steady-state input conditions were established. Output level before the indicated steady-state input conditions were established, provided that CLKAB is LOW before LEAB goes LOW.
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PS8115B
02/03/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................. 65C to +150C Ambient Temperature with Power Applied ................. 40C to +85C Input Voltage Range, VIN ..................................... 0.5V to VCC +0.5V Output Voltage Range, VOUT ............................... 0.5V to VCC +0.5V DC Input Voltage .......................................................... 0.5V to +5.0V DC Output Current ...................................................................... 100mA Power Dissipation .......................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions(1)
Parame te rs VCC VIH VIL VIN VOUT IOH De s cription Supply Voltage Input HIGH Voltage VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V 0 0 VCC = 2.3V High- level Output Current VCC = 2.7V VCC = 3.0V VCC = 2.3V IOL TA Low- level Output Current VCC = 2.7V VCC = 3.0V Operating Free- Air Temperature - 40 Te s t Conditions M in. 2.3 1.7 2.0 0.7 0.8 VCC VCC -6 -8 - 12 6 8 12 85 C mA V Typ. M ax. 3.6 Units
Input LOW Voltage Input Voltage Output Voltage
Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
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PS8115B
02/03/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER
DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C, VCC = 3.3V 10%)
Parame te rs IOH = - 100 mA IOH = - 4 mA VOH IOH = - 6 mA IOH = - 8 mA IOH = - 12 mA IOL = 100 mA IOL = 4 mA VOL IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.7V VI = 1.7V VI = 0.8V VI = 2.0V IOZ(4) ICC DICC VI = 0 to 3.6V VO = VCC or GND VI = VCC or GND IO = 0 One input at VCC - 0.6V, other inputs at VCC or GND VIL = 0.7V VIL = 0.7V VIL = 0.8V VIL = 0.8V VIL = 0.8V VIH = 1.7V VIH = 1.7V VIH = 2.0V VIH = 2.0V VIH = 2.0V Te s t Conditions VC (1) C Min. to Max. 2.3V 2.3V 3.0V 2.7V 3.0V Min. to Max. 2.3V 2.3V 3.0V 2.7V 3.0V 3.6V 2.3V 3.0V 3.6V 3.6V 3.6V 3V to 3.6V 3.3V 3.3V 4 8 45 - 45 75 - 75 500 10 40 750 pF mA M in. VCC - 0.2 1.9 1.7 2.4 2.0 2.0 VCC - 0.2 0.2 0.4 0.55 0.55 0.6 0.8 5 V Typ.(2) M ax. Units
II (Hold)(3)
CI Control Inputs VI = VCC or GND CIO A or B ports VO = VCC or GND
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient and maximum loading. 3. Bus Hold maximum dynamic current required to switch the input from one state to another. 4. For I/O ports, the IOZ includes the input leakage current.
Operating Characteristics, TA = 25C
Parame te r CPD Power Dissipation Outputs Enabled Capacitance Outputs Disabled Te s t Conditions CL= 50pF, F = 10 MHz Vcc = 2.5V 0.2V Typical 41 6 Vcc = 3.3V 0.3V Typical 50 6 Units
pF
4
PS8115B
02/03/98
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH1622601 18-BIT UNIVERSAL BUS TRANSCEIVER
Timing Requirements over Operating Range
Parame te rs fCLOCK tW Pulse Duration D e s cription Clock frequency LE high CLK high or low Data before CLK high tSU Setup time Data before LE low, CLK high Data before LE low, CLK low CLK EN before CLK high Data after CLK high tH Hold time Data after LE low, CLK high Data after LE low, CLK low CLK EN after CLK high Dt/Dv(1) Input Transition Rise or Fall VC = 2.5 V 0.2 V C M in. 0 3.3 3.3 2.3 2.0 1.3 2.0 0.7 1.3 1.7 0.3 0 10 M ax. 140 VC = 2.7 V C M in. 0 3.3 3.3 2.4 1.6 1.2 2.0 0.7 1.6 2.0 0.5 0 10 M ax. 150 VC = 3.3 V 0.3 V C M in. 0 3.3 3.3 2.1 1.6 1.1 1.7 0.8 1.4 1.7 0.6 0 10 ns/V ns M ax. 150 Units MHz
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
Switching Characteristics over Operating Range(1)
Parame te rs From (INPUT) To (OUTPUT) VC = 2.5 V 0.2 V C M in.(2) fMAX tPD tPD tPD tPD tPD tPD tEN tDIS tEN tDIS
Notes:
1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays.
VC = 2.7 V C M in.(2) 150 M ax.
VC = U3.3 V 0.3 V C M in.(2) 150 M ax.
Units
M ax.
140 A B LEAB LEBA CLKAB CLKBA OEAB OEAB OEBA OEBA B A B A B A B B A A 1.8 1.8 1.5 1.5 2 1.2 1.7 2.5 1.7 2.5 5.4 5.4 6.1 6.1 6.7 6.7 6.6 5.9 6.6 5.9
MHz 4.5 4.5 5.1 5.1 5.5 5.5 5.7 4.8 5.7 4.8 ns
5.2 5.2 5.9 5.9 6.3 6.3 6.7 5.3 6.7 5.3
1.6 1.6 1.5 1.5 1.6 1.6 1.6 1.8 1.6 1.8
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PS8115B 02/03/98

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